

module riscv_timer(input rst, input clk, output [31:0] val);

    localparam CNT_1MS = 14'h30d4;      // = 12.5Mhz / 1000

    reg [31:0] timer_val;
    reg [13:0] cnt;

    assign val = timer_val;

    always @(posedge clk or negedge rst) begin
        if (~rst) begin
            timer_val <= 32'h0000_0000;
        end
        else if (cnt == 14'h0000) begin
            timer_val <= timer_val + 32'h0000_0001;
        end
    end

    always @(posedge clk or negedge rst) begin
        if (~rst) begin
            cnt <= 14'h0000;
        end
        else if (cnt == CNT_1MS) begin
            cnt <= 14'h0000;
        end
        else begin
            cnt <= cnt + 14'h0001;
        end
    end

endmodule

